Modern integrated circuit designs allow certain specific arrangements of devices (e.g., N-P-P-N or P-N-N-P arrangements of transistors). These devices in these specific arrangements of devices may have different heights, different structures, and/or different spacing values in between. On the other hand, conventional placement tools only allow placement of standard cells having the same height. In addition, conventional approaches require intensive computational resources as well as human efforts to manually arrange devices having different height values during placement. In an example including devices having different height values, a placement tool may iterate through a plurality of processing with extensive inputs and manipulations by a designer to place these devices.
For example, a placement tool may arrange these devices in a certain pattern but to subsequently find that the pattern violates certain rules or requirements and thus does not result in a legal placement layout or floorplan. Examples of such violations may include a determination that the pattern is not permitted by some manufacturing requirements, a device in the pattern being placed in a prohibited orientation or a device being placed in a location that does not align one or more grids (e.g., poly grids for polysilicon gates, fin grids for multi-gate devices, etc.) of the device (e.g., an instance of a cell) with the one or more corresponding grids defined for the placement layout or floorplan. Other examples of such violations may include a device being placed at a location that fails to observe the site definition (e.g., siteDEF),
In addition, a device may be placed at a location in one of multiple possible orientations where some or all of these multiple possible orientations lead to legal placement of the device. These multiple legal orientations, when coupled with the aforementioned alignment or positioning requirements, further complicate the placement. For example, a device may be placed in a first orientation at a location that results in illegal placement of the device in the placement layout or floorplan. Nonetheless, the same device may be placed in a second orientation at the same location that results in legal placement of the device. In this example, the illegal placement of the device may be fixed by simply rotating the device. Nonetheless, the alignment and/or positioning of the device, when coupled with the orientation, may cause the placement tool to waste much more computational resources to repeatedly trying different placement options before finally arriving at a legal placement result.
The problems of conventional approaches with requiring intensive computation is further exacerbated when a certain arrangement of devices is repeated in a portion of the placement layout. For example, in integrated circuit designs such as memory cells, a pattern or arrangement of devices may be repeated several times to fill a region in the layout. With the conventional approaches, an error in one pattern or arrangement needs to be fixed multiple times so that the repeated patterns or arrangements are legal.
These problems are further exacerbated in advanced technology nodes (e.g., 14 nm and below) that permit only a limited number of legal track patterns and a number of permissible width values. A legal track pattern includes a plurality of routing tracks that are associated with a permissible combination of width values. For example, the advanced technology nodes may require that a routing track associated with 34 nm width cannot be located immediately adjacent to another routing track associated with a width value of 58 nm or greater. Placement tools thus need to address not only the aforementioned complexities but also conform to the limited number of legal track patterns.
Therefore, there is a need for an improved approach to implement placement to address at least the aforementioned shortfalls of conventional approaches.